Esterel EDA>Downloads>Technical Documentation
Esterel Studio Technical Documentation
Categories index
Esterel Language
- Esterel Language Quick Reference Card
- How to Use Esterel interfaces
- An Esterel v7 Primer for Hardware Designers
Design Specification Capture
- Designing with Esterel Studio Architecture Diagrams (version 6.0)
- How To Design a Basic Register Bank Using Esterel Studio
- Correct and efficient handling of numeric data sizes in Esterel
- How to Use Esterel interfaces
- How to organize your multiclock design
- How to Use existing legacy HDL code in my Esterel Project
- Generating efficient hardware with Esterel v7 and Esterel Studio
- An Esterel v7 Primer for Hardware Designers
Design Verification
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Best practice for using signal capture
- How to perform Code Coverage with Esterel Studio
- How to Use Equivalence Checking in Design
- How to Verify Faster And Better With Assertions
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How to use interpolation to prove more assertions
Code & Testbench Generation
- Understanding the HDL code generated by Esterel Studio (version 6.0 and 6.0.1)
- Understanding the HDL code generated by Esterel Studio (version 6.0.2)
- Understanding Esterel Studio Code Optimization
Project Management
- How to generate and use IP packages
- How to install the Esterel Configurator
- How to use an Executable Specification
ESL Flow
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How to integrate Esterel code in CoWare Platform Architect
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How to use Esterel Studio in a SystemC ESL Flow
- How to Reuse Esterel Designed IP in ARM SoC Designer
- How to Insert Statistics Computations in Generated SystemC
- Designing a Hardware Transactor for ZeBu with Esterel Studio: The Example of a CRC Generator-Checker
Product
- Using Esterel Studio 6.0 with MinGW on Windows platform
- Using Esterel Studio 6.0 Graphical Simulator with Visual NET 2005 on Windows platform
