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Getting Started with Esterel Studio 
Getting Started Manual [4.8 MB]
This Getting Started Manual gives a tour of the specification-to-RTL design flow with Esterel Studio. Activities are illustrated with a digital filter example representative of typical applications. This example illustrates:
- Esterel Studio graphical state machines and Esterel textual language modeling
- Control path for communication protocol designs
- Arithmetic and data computation
- Functional verification by simulation and formal verification of assertions
- Complete insertion in the RTL design flow
For an in-depth view of the product and its methodological aspects, please contact your Esterel Technologies representatives who will be happy to propose a training adapted to your needs.
Chapter 1: Introduction
This chapter presents an overview of Esterel Studio user interface, Esterel Studio workflow for SOC/ASIC design, as well as available documentation. You can read about:
- Using Esterel Studio Documentation Set
- Discovering Esterel Studio Workflow
- Presenting Esterel Studio Workspace
- Loading a Project
- Walking through the Filter Project
Chapter 2 : Specification Capture
This chapter describes specification definition, capture, and model design steps to create a digital Filter. In our example, we assume the filter is used in a video system. We start with two modules, a Filter and a Feeder module. The Feeder module reads image words from memory and presents Pixel data to the Filter itself. The Filter performs computation on the incoming stream of pixels and produces a filtered output stream of pixels for a display device. In this chapter, you will learn about:
- Specification Overview
- Model Design
Chapter 3 : Model Debugging
This chapter covers the Esterel Studio functions for checking the design of your model. Debugging is typically a three-stage process, consisting of running coherence check, performing simulation sessions, and launching formal verification analyses.You will learn about model debugging in the following sections:
- Coherence Check
- Model Simulation
- Formal Verification
Chapter 4 : Generating Code
This chapter deals with software code generation in C, SystemC, C++, as well as Register Transfer Level (RTL) code generation in VHDL and Verilog.
Generated code in SystemC, C, or C++ is typically used to export Esterel Studio design into software development environments, compiled simulation for regression testing, and system-level simulation and profiling tools.
Generated HDL — VHDL or Verilog RTL code — is suitable for ASIC and FPGA implementation. Modular compilation allows to split a design into several HDL files and processes. HDL code can be customized for clocks, reset schemes and various netlist speed or area optimization options.
In this chapter, you will learn about:
- Generating C code
- Generating SystemC code
- Generating synthesizable VHDL / Verilog
