Esterel EDA>Services>Esterel Studio Training

Esterel Studio Training

• General information
• Our customers
• Quotes
• Esterel Studio training course
• Agenda

General information

Training location

Training sessions take place at our training center in Villeneuve-Loubet (Nice area - French Riviera) or on customer site.

Materials

Esterel Technologies supplies course-related materials, including:

• Training Manuals
• Reference Cards
• Reference Guide
• CD-ROM including e-version of material above, additional documentation and model corrections

Schedule and class size

• Day 1 - Day 3: 9:00am to 17:30pm
• Day 4: 9:00am to 16:30pm
• Maximum number of participants: TBD

Our customers

We have trained engineers from:

Airbus, CNES, Dassault Aviation, Eurecom, France Telecom, Motorola, PSA Peugeot Citröen, Sagem, Sextant Avionique, STMicroelectronics, Texas Instruments, Thales, Schlumberger, Thomson-CSF Communication.

Quotes

This training was highly enriching. I was really impressed by the instructors and the organization. I also really appreciated the good balance between presentation and exercises.

Mr. Stephane Gaillard, DSP Engineer, Texas Instruments

I really benefited from Esterel Studio training. It gave me the opportunity to discover an original, remarkable and powerful product for building proven embedded systems.

Mr. Bruno Gentil, Advanced Studies Engineer, Thomson-CSF Communication

Esterel Studio training course

Session duration

4 days

Audience

Project Managers

System Architects

Design Engineers

Verification/Validation Engineers

Prerequisites

None

Description

Designed to give participants solid and durable foundations in synchronous modeling principles.

Topics include the language genesis and fundamentals, methodological guidelines and Esterel Studio design flow.

Attendee profiles determine the emphasis on specific topics (architectural design, module design, design validation, etc).

In order to ease the assimilation of the concepts, the training technique relies on an alternation between the theory and a variety of workshop based on different stimulations (assessments via labs, quiz, work group).

Objectives

Gain knowledge of Esterel language and graphical state machines.

Acquire the suitable modeling reflexes via significant programming practical experience.

Assimilate methodological guidelines.

Be able to start the design and development of a project using Esterel Studio.

Agenda

Day 1, AM session

Course introduction

Introduction to the synchronous approach

Project structure

Lab session

Day 1, PM session

Basic Signals

Safe State Machine (SSM) design

Simulator

Lab session

Day 2, AM session

Esterel language Basis

Safe State Machine (SSM) design

Day 2, PM session

Signals and expressions: The equational level

Lab session: Design of a multi-clock FIFO

Day 3, AM session

SSM language advanced notions

Esterel language advanced notions: Declarative and Imperative

Model Verification

Day 3, PM session

Formal Verification

Sequantial equivalence check

Lab session

Day 4, AM session

Data

Data, interface and module units

HDL generation

Code traceability

SystemC/C/C++ generation

Executable specification generation

Day 4, PM session

Application Project: AXI memory

Review and discussion