Esterel EDA>Customers>Usage and Benefits

What are the Benefits of Esterel Studio?

Time to Market

• Early validated executable specs are obtained much faster than RTL coding and cut your time to market by at least 30%.

Communication

• Communicate within and between teams using formal and easy to understand models: 70% of serious bugs are specification-related and can be detected in early design stages.

Quality

• Formal verification of safety properties stress designs and are unmatched at detecting corner-case problems. Early and formal verification can reduce the number of bugs escaping to system-level simulation by up to 50%.

RTL Cost-reduction

• Automatic efficient synthesizable RTL generation saves coding time, and, most importantly, ensures 100% identical behavior between Esterel Studio Executable Specification, RTL, and C-based models.

Who uses Esterel Studio?

Micro-architects

Micro-architects design executable specification and capture their micro-architecture with Esterel Studio. They distribute Executable Specifications together with paper documents as a reference shared with designers, verification engineers and remote teams, together with some design assertions the implementation should meet. The Executable Specification Player, available free of charge, enables remote teams to exercise executable specifications.

RTL Designers and Verification engineers

RTL Designers use Esterel Studio Executable specifications that they refine refine into design specification performing remaining optimizations, . They also check IP properties using the Design Verifier, generate RTL, connect to synthesis and back-end. Esterel Studio generated RTL is compliant with all synthesis and DFT tools. Esterel Studio IP can also smoothly go to accelerated verification platforms. Designers and Architects keep the Esterel Studio specification as a single always up-to-date reference.

System Architects

System architects use Esterel Studio generated SystemC to incorporate IP into their System Level exploration and virtual prototypes environment. System validation engineers also use Esterel Studio for specific tasks, incl. proofs of specific system properties, worst case dimensioning, chip-level validation. Smart card and security related application architects use Esterel Studio for systems specification and modelling.