Esterel EDA>Products>SystemC Code Generator

SystemC code generation

The Esterel compiler generates cycle-accurate SystemC code fully compatible with OSCI SystemC 2.1. The generated SystemC code is used to simulate the synchronous hardware designed with Esterel Studio exactly as in a zero-delay RTL simulation, but with much greater speed. 

Generate SystemC for fast system simulations

The generated code has the same interface as the generated RTL. Esterel Studio generates SystemC that comes in two flavors, signal-based or cycle-based.

• Signal-based implementation has a combinational process and a clocked process exactly as in RTL. It simulates slower than cycle-based but handle safely all components in any contexts even in presence of combinational paths from inputs to outputs
• Cycle-based implementation has clock sensitivity only and no input sensitivity. It simulates faster than signal-based code, but it requires setting appropriate delays to correctly schedule the simulation of the various components when there are combinational paths from inputs to outputs.

SystemC options

The SystemC code generator supports the following options:

• Clock and reset name setting Clock active edge: rising or falling
• Synchronous or asynchronous reset Reset active level: high or low
• Display of combinational paths (from inputs to outputs)
• Use of C types instead of SystemC types for interface signals
• Signal record instrumention (generation of a trace file at run-time that can be played back in Esterel Studio for debug purpose)