Esterel EDA>Products>Simulator

Simulator

Create an interactive simulator in one click to debug the specification, record test scenarios and simulation sessions, export to your favorite VHDL or Verilog simulator. Automatically create an HDL testbench from Esterel Studio saved simulations and co-simulate your specification together with generated RTL.

With the step-by-step cycle-highlight, all views of your design, including design tree, graphics and textual views are consistently updated at once to show executed statements, fired transitions and reached states. This enables easy spotting of areas of interest and fast navigation between them.

The simulator comes with extensive controls, direct interactive input, observation of all I/O and local signals, design assertions checking, selection of dynamic checks. All your simulation work can be saved and reused thanks to the session recorder/player, including simulation comment annotations to help others understand the dynamics of your design.

Enabling code-coverage highlight during simulation works all the same: all graphical and text objects keep track of a coverage status while color highlighting is showing coverage progress. Coverage measure is summarized at the end in a report.

Full navigation history, workspace layout, and generally all user context is saved between sessions: modern user interface features and shortcuts contribute to free your mind from tedious bookkeeping tasks and let you concentrate on specification and design itself.

You can simulate in your favorite RTL simulator the VHDL or Verilog generated from Esterel Studio specification. You can trace back all behavior from RTL simulation to Esterel Studio source by co-simulating and visualizing Esterel Studio simulation state during RTL simulation.