Esterel EDA>Products>RTL Code Generator

RTL Generation

Esterel Studio includes VHDL and Verilog code generation, directly from the executable specification. Design micro-architecture and optimization is directly done at Esterel Studio level, and RTL is automatically generated. This way, the reference specification and RTL are always synchronized.

Esterel Studio design is consistently reported 3 to 5 times more compact than HDL design. Extensive control over the RTL generation generation process is available to ensure generated RTL fits all contexts and existing tools of your design flow. Esterel Studio generated RTL is efficient, there is no quality loss over hand coded RTL.

Esterel Studio generates both VHDL and Verilog code

Esterel Studio can generate VHDL or Verilog module per module, to split designs and facilitate hierarchical synthesis. Code generation options and optimization criteria are also defined module per module, to reach the best speed-area tradeoff. It is also possible to add already available RTL, third party memories, or DesignWare IP blocks to your design.

Modular RTL code generation

RTL generation can be customized in many respects: synchronous or asynchronous reset, rising or falling clock edge, endian-ness coding, signals active high or active low, coding style, optimization level, assertions propagation for dynamic checks, libraries, connection to host language (VHDL or Verilog) supplied data objects found in imported packages, code instrumentation for co-simulation, traceability level between RTL and Esterel Studio source and more.

RTL generation can be customized for synchronous or asynchronous reset

Traceability between RTL and Esterel Studio is supported both in the form of documentation and as interactive instrumentation showing the correspondence between Esterel Studio objects and generated RTL. Such instrumentation and tooling is key in understanding back-end diagnostics, critical paths, or ECOs and modifying Esterel Studio source as needed. Labeling and names propagation mechanism are used to easily find generated RTL components and operators and allow user driven mapping onto your own library operators.

The user interface provides a specific browsing mode using all traceability instrumentation to identify the Esterel Studio origin of RTL variables and nets, or show all RTL code related to an Esterel Studio object.

Complete traceability and explanation of correspondence between RTL and Esterel Studio source.

When performing design refinement with synthesis in-the-loop iterations, one has to cope with critical paths diagnostics and update Esterel Studio design, like say, add a pipeline stage in a computation. To help with this process, visualization of critical paths directly in Esterel Studio source is supported. Esterel Studio allows to display critical paths module per module to accomodate when critical paths cross top-level modules boundaries.

Display of critical paths reported by from your usual synthesizer within Esterel Studio model.