Esterel Integrates Studio Technology into ARM RealView Tools

MOUNTAIN VIEW, California, and ELANCOURT, France. June 6, 2005. Esterel Technologies today announced a solution to integrate IP (Intellectual Property) blocks designed using Esterel Studio into system-level virtual prototyping environments using ARM® RealView® tools with MaxSim™ technology.

The combined solution will enable developers of ARM technology-based System-on-Chips (SoCs) to quickly insert their Esterel Studio IP executable specification into an ARM RealView system model. The Esterel Studio and ARM RealView co-simulation capabilities enable thorough IP debugging in a system context. Microarchitects and designers can further explore their IP microarchitecture options, measure real impact on system performance, and choose the optimal IP design to meet system requirements.

Esterel Studio's automatic generation of implementation-quality RTL not only saves RTL coding time, but also ensures that IP specification, virtual prototyping, and implementation views will be consistent at all stages of the design flow.

Today, high-end SoC communication and computing requirements translate into complex IP designs that must be optimized for system performance; and time-to-market pressure makes it necessary to quickly configure IP for various SoC derivatives and peripheral mixes. When IP optimization is performed at the RTL detailed design stage, changes must be reported to the virtual prototype level to reassess system performance. This late, and costly, process limits architecture exploration to a bare minimum.

In contrast, thanks to Esterel Studio and ARM RealView simulation technology integration, IP optimization can be performed early, in a tight loop with system-level prototyping. First, Esterel Studio's capability to formally describe and verify hierarchical Finite State Machines (FSM) shortens microarchitecture design of such components as bus and peripheral interfaces, communication protocols, memory controllers, power management, and peripheral cores. Then, integration of Esterel Studio's flexible microarchitecture description within RealView simulation technology's fast system profiling enables quick IP optimization and true architecture exploration. Finally, Esterel Studio's RTL generator directly connects IP specifications to the implementation flow.

“This integration provides our customers with a seamless design flow, from system-level virtual prototyping level to final IP optimized implementation,” said Eric Bantegnie, CEO of Esterel Technologies.

“Esterel Studio technology's formal IP specification and finite-state machine debugging environment complements the ARM RealView technology,” said Chris Lennard, ESL technical marketing manager, ARM. ”The RealView simulation technology's powerful profiling engines enable Esterel Studio technology users to quickly optimize their design before flowing directly to component implementation.”

Esterel Studio is a comprehensive toolset for describing and verifying IP executable specifications. It includes an editor, simulator, and assertion formal verification capability. C and C++ code generators enable connection to the MaxSim system-level virtual prototyping environment. VHDL and Verilog code generators automatically turn an IP reference specification into quality implementation.

ARM RealView tools with MaxSim technology provide a comprehensive toolset for fast modeling, simulation, and debugging of complex SoC designs, ideal for system-level architecture exploration and pre-silicon embedded software development.

Demonstrations of Esterel Studio's IP design flow optimized with ARM RealView technology for system-level performance analysis can be seen in the ARM booth number 1309 at DAC 2005, June 13-16, in Anaheim, California.

About Esterel Technologies

Esterel Technologies tools create unambiguous specifications that produce correct-by-construction software designs and hardware designs that can be implemented automatically. SCADE Suite™ is the de facto standard for the creation of safety-critical embedded software in the civilian avionics industry. Esterel Studio™ enables embedded hardware designers to create a golden specification model that can be implemented automatically in VHDL, Verilog, C, and C++.

Esterel Technologies is a privately held company with headquarters in Mountain View, California, USA, and Elancourt, France, with sales offices in Germany, the United Kingdom, and China.

For more information, visit the Esterel Technologies website.

Contact:

Jean-François Baggioni, Esterel Technologies

Phone: +33 (0)4 92 02 40 41

Email: jean-francois.baggioni@esterel-technologies.com

ARM and RealView are registered trademarks of ARM Limited. MaxSim is a trademark of ARM Limited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.

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