Esterel Technologies Announces "Design for Verification" With Esterel Studio 5.0

Specification to RTL or C, Correct by Construction

MOUNTAIN VIEW, Calif. and ELANCOURT, France (August 25, 2003)

Esterel Technologies today announced Esterel Studio™ 5.0 a comprehensive tool suite for the design and verification of complex consumer and multimedia SoCs.

Esterel Studio 5.0 lets the user capture a design specification and then automatically generate the hardware description in HDL-RTL or C. Combining advanced simulation methods with a sophisticated proof engine, high level primitives and hierarchal state machines, Esterel Studio 5.0 builds verification into the design process, eliminating the majority of functional errors right at the start of the design process and allowing engineers to develop a golden reference model in text and/or graphics with a complete path to correct-by-construction, automated implementation. Early adopters have already used the technology for production designs and FPGA prototypes for such applications as memory and peripherals controllers, D/I caches, battery management, protocols, and smart card secure embedded applications.

By using Esterel Studio we are able to specify a control-intensive design that could automatically be implemented in the hardware of the FPGA fabric or in software running on the PowerPC processor embedded in the Virtex-II Pro platform FPGA, allowing HW/SW exploration, co-synthesis and formal verification. The promise of this technology is to help Xilinx customers quickly and easily develop IP blocks and check their Core Connect bus conformance. The Esterel Studio product is extremely powerful and the benefit of its hardware/software co-design coupled with its correct-by-construction methodology can improve design productivity and dramatically cut verification costs said Ivo Bolsens, Xilinx CTO and head of Xilinx Research Labs.

Our Esterel Studio early adopters such as Texas Instruments, STMicroelectronics and Xilinx have been able to achieve very impressive results. With Esterel Studio 5.0 they can create a formal and unambiguous design specification that greatly improves communication between team members, including hardware/software team understanding and information sharing between customers and suppliers. Our users are reporting up to a 40 % savings of traditional verification cost and effort and up to 100 X productivity improvement in implementing late stage design specification changes because the change can be made to the golden Esterel Studio 5.0 specification model and then automatically re-implemented, said Eric Bantégnie, CEO of Esterel Technologies.

The Esterel Studio 5.0 tool suite includes an editor, simulator, assertions verification, and cumulative state space coverage of tests, VHDL, Verilog or C, C++. A SystemC code generator will be available later this year.

Esterel Studio is a very flexible solution that automates your implementation and also allows you to begin verification very early in the development process. TI began using early versions of the product in the late 1990s for modeling a new DSP megacell for a wireless phone. Now, with ES 5.0, we can also prototype FPGAs to run large applications and benchmark architecture trade-offs prior to starting the production design, said Gael Clave, Modeling and Verification Manager, Wireless Terminal Business Unit, Texas Instruments, France.

The powerful state machine capability, Safe State Machines, supports unlimited hierarchical nesting and concurrency plus state transition descriptions. High-level graphical descriptions are complemented by Esterel Studio's textual language descriptions for data description and dataflow logic. This unique combination and the elegance of the high-level primitives makes design specification initial capture up to 4 times faster than RTL coding.

The Esterel Studio 5.0 Simulator detects specification errors by executing the design during the design specification phase. The simulator is a complete toolset that can operate both interactively and in batch mode. It includes a waveform display and a ModelSim gateway. Additionally, through a C API, the Esterel Studio simulator can be easily connected to any other HDL simulator.

Esterel Studio 5.0 includes a robust proof engine, the Design Verifier* which validates the design by proving that the required system properties and assertions hold in all the possible cases. Each error found is complemented by a simulation trace automatically fed into the simulator for immediate diagnosis and correction.

Esterel Studio 5.0 is available in LAN and WAN configurations with one-year time-based licensing starting at US $33,000.

*Design Verifier powered by Prover Plug-In. Prover Plug-In is a trademark of Prover Technology AB in Sweden, the United States, and other countries.

About Esterel Technologies

Esterel Technologies solves the problems of critical design and verification with complete design for verification tool suites supported by the power of abstraction and synchronous languages. Esterel Technologies tools create unambiguous specifications that produce correct-byconstruction automated implementation. Today, SCADE Suite is the de-facto standard for the creation of safety-critical embedded software in the civilian avionics industry and SCADE Drive is the emerging standard for the creation of critical-embedded software in the automotive industry. Esterel Studio allows embedded hardware designers to create a golden specification model that can be implemented in RTL or C.

Esterel Technologies is a private company with funding by Intel Capital, Galileo Partners, Thales Avionics and other leaders with headquarters in Mountain View, California USA, and Elancourt, France. An international company, Esterel Technologies also has offices in Germany, UK and China.

For more information: www.esterel-technologies.com

Contacts:

Esterel Technologies and US PR 650-641-1706

linda.prowse-fosler@esterel-technologies.com

PR agency in Europe: Carne Communications

Jeremy Carne

Phone : +44 (0)20 7384 2500

jeremyc@carne.com

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