Esterel EDA>News and Events>Esterel Studio New Version
What's new in Esterel Studio version 6.0
Esterel Studio version 6.0 features major improvements in all areas of the product: design specification capture, design verification, project management, and RTL or SystemC code generation. All these enhancements contribute to make the ESL synthesis with Esterel Studio a productive and ready to use solution.
Whats new in Esterel Studio version 6.0
Architecture diagrams editor
The new architecture diagrams editor enables to capture the structure of the design, with its different blocks, ports, and connections. It provides a clear view of the component micro-architecture which is particularly useful for navigation during design or simulation. Architecture diagrams are hierarchical, and the behavior of their basic blocks is described using standard Safe State Machines and Esterel code. The editor takes full advantage of Esterel stuctured interfaces and ports to help the user construct compact diagrams in a few clicks.
A strong point about this editor is its full support of dynamic visualisation of blocks interactions during simulation with highlights on blocks and connections where signals are communicated. This enables to visually focus on where the reactions are taking place and get to the behavior detailed code just a click away. Although waves are also provided, dynamic highlight and debugging at Esterel source level is much more comfortable than going through RTL simulation testbench and waves analysis, while not requiring any setup overhead.
Architecture Diagrams editor
New early ESL synthesis performance estimation tool
When dealing with ESL synthesis tools, designers and architects need a quick feed-back on the characteristics of the circuits they build. The descriptions at ESL level are more abstract and compact, but the engineers are less used to what logic the new tools will create from high-level descriptions. Going all the way through synthesis to assess circuit performance may be an overkill and too long to set up at early stages of design. This is why the Esterel Studio early ESL synthesis performance estimator has been designed. It returns a quick estimate of circuit performance indicators, similar to those returned by synthesis, but much quicker:
- Allocated registers
- Area consumption estimate
- Max estimated delay path
- Operators count
The performance estimator is a great help to quickly compare micro-architecture choices, balance between area and speed, and to check that powerful operators and arrays do not generate unwanted logic. Tracing back to the design costly parts is made very easy, and beginers can reassure themselves as they design that they keep on track with the performance targets. Esterel Studio performance estimator returns results in html and comma speparated format for spreadsheets.
ESL Synthesis Performance Estimation
Other enhancements
The Source Code Coverage is redesigned, to allow better reporting, incremental coverage measurement sessions, save, reload, improved batch mode support, and better interactive simulation feedback. It is very productive and recommended to perform code coverage analysis at Esterel Studio level before any RTL work.
The Design Verifier has been enhanced to integrate state of the art new model checking algorithms, including interpolation, induction, and mixed strategies. When properties are falsified, the automatically generated faults scenarios are better handled through dedicated menus, to promote them as future non-regression tests etc. The new strategies have been tested on more than a hundred designs, many of which being real customer ones, and it clearly shows the new algorithms yield outstanding speed-ups on complex assertions.
Interpolation algorithm boosts Formal Verification
The Design Reporter outputs in html and rtf are completely restyled, and now produce a comprehensive report more compact and readable.
SystemC code generator has been optimized for simulation speed, supports more configuration options, and most importantly now support modular SystemC code generation which is mandatory for multi-clock designs.
VHDL and Verilog code generators support the signal record instrumentation for multi-clock designs, allowing the use of other RTL level analysis tools durng simulation. Signal equations order in seq blocks are checked for consistency, and assertions can be directly generated in the target code for other tools to use.
The SPIRIT IP-XACT export now supports bus interface definitions and multi-clock designs. The software executables include an Loose Generator Interface (LGI) generator, and many new options have been added to SPIRIT packaging, to allow for multiple simultaneous target languages, prefix definitions, target directories, etc.
