Esterel EDA

What is the difference between Esterel, VHDL, and Verilog?

Esterel brings unique productivity and quality enhancements over traditional hardware description languages. Esterel provides state-of-the art data support: exact arithmetic, automatic sizing, incremental pipelining, slicing, and multidimensional arrays.

On the control side, Esterel brings unique temporal primitives and hierarchical FSM. Concurrency modeling is as easy as in RTL, and sequencing behaviors is as easy as in C programming.

Together, this makes Esterel a tool of unmatched modeling productivity for bus and peripheral interfaces, communication protocols, memory controllers, power management, and core peripherals.