Esterel EDA

What is Esterel Studio?

Esterel Studio™ is a toolset for specifying, verifying, and implementing hardware IP blocks. It includes an editor, to support the Esterel textual language, and the graphical Safe State Machines (i.e., Safe finite State Machines of Esterel Studio). The toolset comes with a simulator, formal verification engines, and a sequential equivalence checker. C, C++, and SystemC code generators enable connection to system-level virtual prototyping environments. VHDL and Verilog code generators automatically turn IP reference specification into implementation-quality RTL.™