Esterel EDA>Frequently-Asked Questions

Esterel Studio

• General
  • Who are Esterel Studio main customers?
  • What is the Esterel language?
  • What is Esterel Studio?
  • How is Esterel Studio used?
  • Why should I use Esterel Studio?
  • What are the advantages of using Esterel Studio?
• Language
  • What is the difference between Esterel, VHDL, and Verilog?
  • Why are Esterel Studio FSMs more powerful than traditional flat FSMs?
  • What is the level of abstraction supported by Esterel?
  • Are technical papers on Esterel and design problems available to read online?
• Tools
  • How does Esterel Studio fit in my flow?
  • What is the Esterel Studio Sequential Equivalence Checker?
  • How can I be sure that generated RTL and generated C have the same behavior?
  • Is there a connection between Esterel Studio™ and the public Esterel from X, Y, Z university?
  • Where can I get an academic version of Esterel Studio?
  • Can Esterel Studio generate both ASIC and FPGA RTL?
• Synthesis
  • Can I read generated Verilog or VHDL?
  • Can I reuse legacy RTL in an Esterel Studio project?
• Formal Verification
  • What type of formal verification does Esterel Studio support?
  • How do I use the formal verification in Esterel Studio?
• Miscellaneous
  • What are the supported platforms?

  Frequently-Asked Questions