Esterel EDA

How does Esterel Studio fit in my flow?

Esterel Studio seamlessly integrates your design flow, thanks to proven compatibility and connections to all other EDA tools along the design flow:

• Connects to system-level virtual prototyping environments (i.e., ARM® RealView® MaxSim™).
• Generated code is compatible with RTL and Gate-level simulators of major ASIC and FPGA simulators, including ModelSim™, NC-Sim™, Scirrocco™, or VCS™.
• Supports cosimulation-that is, the Esterel Studio simulator interacts concurrently with any HDL simulator.
• RTL-generated code is compliant with major synthesizers: Synopsys Design Compiler FPGA, Xilinx ISE, Actel Libero™, Synplicity Synplify®, Synopsys Design Compiler®, or Mentor LeonardoSpectrum™.
• Generated RTL compliant with DFT ATPG tools including Synopsys TetraMax™, and Mentor FastScan™.