Esterel EDA

How do I use the formal verification in Esterel Studio?

The Design Verifier is completely integrated into the Esterel Studio IDE, allowing users to be productive immediately. The Design Verifier does not need any test benches or test vectors; it performs formal analysis and model checking of the design. Thus, it can be used right from the start of the design flow.

When the Design Verifier finds a potential fault, it produces a simulation scenario leading to the falsification of the assertion so that it can easily be simulated and the error can be diagnosed and corrected.