Esterel EDA

Can I read generated Verilog or VHDL?

Machine generated code is not as easy to read as hand written RTL. There are several reasons. First, the source code is at a higher level than standard Verilog/VHDL and its translation requires non-trivial scheduling of Verilog/VHDL actions. Secondly, the generated RTL code undergoes sequential and combinational optimization in order to create efficient circuits, which is the goal we pursue. In exchange we raise the abstraction level, allowing our customers to work using more dynamic, sharable, and executable specs as opposed to using a structural RTL representation.

Nevertheless, while reading the code should not be necessary most of the time, it may be required for specific tasks such as critical path visualization, ECOs, and some aspects of SoC validation. Esterel Studio includes a dedicated traceability mode that allows to perform bidirectional correspondence between RTL and Esterel objects.