Categories index

• Esterel Language
• Esterel compared to Verilog, VHDL
• System Level Design (ESL)
• Scientific, Synchronous Programming
• Applications, Methodology
• Books

Authored by Gerard Berry

This document presents Esterel in a precise, yet informal, way to help in making most users comfortable with using the language and system.

Authored by Dan Downs

This document presents some of the real world coding benefits of using Esterel. walking through the process of designing a small control circuit in the two languages. It gives an illustration of what Esterel EDA Technologies is talking about when we say that Esterel code is easier to read and understand and maintain.

An overview of the Esterel language and coding style, using the example of a 4-bit parallel-to-serial converter. The converter is coded in Esterel and in Verilog, and differences are explained.

An overview of the Esterel language and coding style, using the example of a 4-bit parallel-to-serial converter. The converter is coded in Esterel and in VHDL, and differences are explained.

ICCAD paper - Authored by: Gérard Berry (Esterel Technologies) - Michael Kishinevsky (Intel) - Satnam Singh (Xilinx)

Authored by Stephen Edwards, Department of Computer Science, Columbia University, New York

This paper proposes three techniques aimed to improve the quality of the input to logic synthesis to produce better results.

Authored by Gerard Berry.

This book draft is intended for the users of Esterel who want to understand the underlying language and semantics design, and also for readers who are interested in language semantics.

Authored by Gerard Berry.

This paper informally presents the theoretical and practical foundations of synchronous programming of reactive systems, mostly focusing on the Esterel language.

Authored by Charles Andre, University of Nice-Sophia Antipolis

A Safe State Machine (SSM) is a visual synchronous model. SSMs are devoted to programming control-dominated software or hardware systems. SSM is much more than a Finite State Machine; it supports hierarchy, concurrency and preemption. A section in this paper deals in particular with the operational semantics of SSM: the syntax of SSM is precisely defined, and the way a reaction is computed is given.

Authored by Nicolas Halbwachs

A Tutorial and Commented Bibliography.

Authors: S. Bernardi, S. Lebailly, Texas Instruments, B. Blanc, G. Berry, J. Dormoy Esterel Technologies

This paper describes a video application and won the best paper award at the SAME Conference 2004.

Authors: G. Dubost, Texas Instruments, S. Granier, G. Berry, Esterel Technologies

Authored by Laurent Arditi (Esterel Technologies) - Gerard Berry (Esterel Technologies) - Mike Kishinevsky (Intel)

Presented at FMCAD 2004, November 14-17, Austin, Texas

Compiling ESTEREL, the Definitive Reference

Authors: Potop-Butucaru, Dumitru, Edwards, Stephen A., Berry, Gerard

Designed as the definitive reference on the compilation of the Esterel synchronous reactive real-time language, Compiling Esterel covers all aspects of the language. The book includes a tutorial, a reference manual, formal semantics, and detailed technical information about the many techniques used to compile it.

Esterel is based on the simple idea of a software language that has a synchronous model of time. That is, the execution of the program is divided into discrete instants, and statements are either guaranteed to execute in a single instant, or take multiple instants as requested by the programmer. Suitable for programming safety-critical real-time systems, Esterel and its model of computation have found use in industrial applications such as avionics, integrated circuit design, and other safety-critical environments.

Written for: Researchers as well as advanced developers will find this book essential for understanding Esterel at all levels. While this book does not assume prior knowledge of the Esterel language, readers will appreciate having prior knowledge of programming language semantics and compiler technology, along with some familiarity with synchronous digital hardware design.