Examples index

• Mono-clock FIFO
• Multi-clock FIFO
• Simple Register Bank
• Clock Domains Synchronizers
• Cyclic Redundancy Check (CRC)
• Standard Interfaces

Mono-clock FIFO

This is the Esterel Studio design of a simple generic synchronous mono-clock FIFO.

Download Mono-Clock FIFO

Multi-clock FIFO

This is the Esterel Studio design of a simple generic synchronous multi-clock FIFO.

Download Multi-Clock FIFO

Simple Register Bank

This is the Esterel Studio design of a simple register bank.

Download Simple Register Bank

Clock Domains Synchronizers

The multi-clock designs provided here implement, simulate and formally verify a two-phase and a four-phase handshake push synchronizers used to safely transfer information between asynchronous clock zones by correctly taking care of meta-stability issues. The two-phase synchronizer is more complex but has a shorter latency than the simpler four-phase synchronizer.

You can read the two-phase multiclock synchronizer and four-phase multiclock synchronizer Esterel v7 specification documents, authored by L.Arditi, G. Berry (Esterel Technologies 2005-2007), and M. Kishinevsky (Intel Strategic CAD Lab). These documents are included in the zip files.

The four-phase synchronizer is also described in the following paper: R. Ginosar, Fourteen Ways to Fool Your Synchronizer, in Proc. 9th IEEE Int. Symp. on Asynchronous Circuits and Systems, pp. 89 — 96, May 2003. The paper is available in the project directory and project tree as Ginosar.pdf and at the following Internet address: http://www-ee.technion.ac.il/~ran/publications.html.

Download the two-phase synchronizer

Download the four-phase synchronizer

Cyclic Redundancy Check (CRC)

This is the Esterel Studio design of a Cyclic Redundancy Check (CRC). It consists in a CRC code generator and the associated checker, which share a common CRC generator/checker core. Because it is intended for Esterel programming learning purpose, the example is voluntarily kept simple. For instance, the CRC generator polynomial is an Esterel constant, not an input or a set of selectable constants. However, interested readers may modify the design to make the CRC function more parametrizable.

Download Cyclic Redundancy Check (CRC)

Standard Interfaces

Here you can download some commonly used standard interfaces templates:

• Download OCP interfaces for each of the six OCP signal groups. The input and output directions are all from the point of view of the Master. They can be used for OCP master devices. For OCP slave devices and for the system interface, use the mirror of each interface.
• Download PCI interfaces for the peripheral side of the PCI bus. Because of the PCI bus heavy use of bidirectional signals, the interfaces leave the PCI IO block as a separate block and provide separate read, write, and tri-state control signals. A Verilog module PCI_IO is provided as a sample of a behavioral implementation of such an IO pad ring
• Download AXI interfaces for each of the five AXI channels. The input and output directions are all from the point of view of the Master. They can be used for AXI master devices. For AXI slave devices, use the mirror of each interface.