Job Description

You will integrate our R&D team and will be in charge of the specification, architecture and development of our Formal Verification modules included in Esterel Studio.

You will manage the technical interactions with our formal verification engines technologies providers. More precisely, you will be in charge of: writing Statement-of-Works, integrating new engines, evaluating new technologies, identifying new partners, etc.

You will also improve our existing Formal Verification customer-oriented methodology for more widespread formal verification deployment. In this context, you will be part of our Expert Group and will work closely with our consultants and customers.

The position is available at our Villeneuve Loubet (06) France office.

Skills and Competencies

Required

• Combined knowledge of formal methods (model checking, abstraction refinement techniques etc), tool development (C++ on Windows/Linux/ Solaris), and a good understanding of hardware design and micro-architecture.
• Excellent English, written, and oral communications skills required

Additional Skills

• Experience with design management tools like CVS, etc.
• Industrial experience in the field is a plus.
• RTL design experience is also a plus

Education:

• MS, or Ph.D. in Electrical or Computer Engineering

Job Description

Validation and verification of a Multi-media wireless SoC based on multi-processors architecture.
Integrated in a validation team, the project consists in:

• Understand design specifications and work on associated validation plans.
• Design and implement validation suites for ARM and DSP processors in order to exercise and verify critical paths in hardware design.
• Participate to the development of functional validation plan for:
  • Sub-system, modules and peripherals integration (registers accesses, interrupts, DMA transfers)
  • System verification (scenario, application)
• Run these tests on the design and debug it using simulation environment : Full RTL/Gate simulation, Hardware accelerator and final Silicon platforms.
• Find and identify hardware bug and plan solutions with spec/design owners.

Candidate Profile

• Master degree (Engineer) or PhD with 4 years of experience in Microelectronic design.

Skills and Competencies

Required

• Hardware Simulation and debugging on hardware accelerator platforms and RTL/Gate simulation using Modelsim (or others)
• C, C++, Assembly software development for validation of ASIC/SOC at system level
• Language: Good english

Would be plus

• Knowledge in DSP and ARM architectures
• Knowledge of a JTAG general purpose debugger would be a big plus

Job Description

You will be involved within Esterel Technologies in a team specialized in the design and development of FPGA circuits intended to implement prototypes of ASICs.

Your role will be to verify and develop FPGA prototypes based on existing RTL designs for ASIC targets (silicon). The technical perimeter of your responsibilities will be to participate to the functional verification, the front-end design, and the implementation/integration of FPGA prototypes.

The position is based in Villeneuve-Loubet (PACA, near Nice)

Candidate profile

• Master degree (Engineer) or PhD with a minimum of 5 years of experience in FPGA and/or ASIC designs (Particularly on front-end design, verification (pre-silicon), and validation (post-silicon / laboratory)

Skills and competencies

• Experience in design with Vhdl/Verilog as well as synthesis for FPGA and/or ASIC targets
• Experience in RTL/Gate simulation (Modelsim or NC-Sim) for verification purpose, and Lab simulation on silicon/fpga for validation purpose
• Experience in porting ASIC designs to FPGAs would be a big plus
• Fluent or good English speaking

Job Description

You intervene within a team specialized in digital design for wireless applications.
Your role is to implement hardware solutions which will allow to test manufacturing defects on chips.
You are responsible for the whole flow of DFT, from the choice of the strategy to the creation of the tests vectors.

Candidate Profile

Master degree (Engineer) or PhD with 4 years of experience in Microelectronic design.

Skills and Competencies

• Knowledge of VHDL and/or Verilog languages
• Knowledge of ATPG (Automatic Test Patterns Generation)
• Knowledge of Transition Fault Testing (TFT) methodology
• Experience in BIST synthesis
• Knowledge of dedicated tools for DFT (Fastscan/Tetramax, MBISTArchitect, DFT Compiler, TestKompress,…)
• Experience in digital synthesis (Design Compiler) and scan insertion
• Rigorous and dynamic personality
• Language: Fluent in english

Internship Subject

• Creation of automatic demonstrations of Esterel Studio software to be downloaded from our website

Internship description

In order to promote Esterel Studio on the web, we wish to produce and publish on our website and on industry portal a few short automatic demonstrations for download.
The demonstrations will illustrate the main functions of the product, modelling, simulation, and code generation. The demonstrations will be packaged with documentation, an audio track recorded by a native English speaker. Ideas to trigger interest like incorporating video sequences, etc… will be encouraged.

This internship is for a creative type person, with good ability to communicate with our R&D team.
It is not technically complex, but requires precision and care.

Trainee Profile

• Engineering school student (Electronics or Computer Science - preferably 2nd year).
• Programming and web knowledge

The position is based in Villeneuve-Loubet (PACA, near Nice).
Send your resume to: eda@esterel-technologies.com

Job Description

This job relates to a position within a team who is in charge of the development of the wireless ICs using the leading edge of the technology.
As part of a very dynamic engineering team, you will be responsible of developing, specifying and verifying System-On-Chip architectures for mobile phone devices.

This mission consists of:

• Implementation of high complexity digital basebands in 65 and 45 nm technologies, with low power techniques and usage of most up to date design flows
• Work with teams designing high-speed ASICs
• Identifying and developing a validation and verification framework for the DBB SOC architecture

Candidate Profile

• Engineer in electronics with 3 years of experience minimum

Skills and Competencies

• Design/Methodology Experience with Static Timing Analysis using Primetime-Primetime-SI
• Timing closure, Signal Integrity, OCV, timing constraints development, timing libraries, Clock tree synthesis analyze
• Knowledge of Perl and Tcl or other programming language mandatory
• Experience in SoC backend designs
• Rigorous and dynamic personality
• Good communication skills (English)

Job Description

Integrated in a validation team, the project consists in understanding design specifications and working on associated validation plans:

• Develop test cases in C language, in Assembler (for ARM and DSP processors) or in E language (Specman environment) in order to exercise all hardware path in the design:
  • Sub-system, modules and peripherals integration (registers accesses, interrupts, DMA transfers)
  • System verification (scenario, application)
• Run these tests on the RTL and debug it using software-hardware co-simulation environment, full RTL or gate environment, Specman environment
• Find and identify hardware bug and plan solutions with spec/design owners

The position is based in Villeneuve Loubet (PACA, near Nice)

Candidate profile

• Master degree in Electronics with experience in mobile wireless systems
• Minimum experience of 3 years

Skills and competencies

• Software development: C language, Assembler, Debugger
• Hardware simulation and debug: RTL simulation, Modelsim
• Tools : verification tools (Modelsim), debugging tools for silicon validation (Code Composer, Lauterbach)
• Validation tool: Specman
• DSP architecture: TI DSP C54, C55
• ARM architecture: ARM9, ARM11
• English – high level required
• Very good communication
• Autonomous and pro-actively team player

Job Description

You will be part of a dynamic design team which responsibility is to develop a chip subsystem made of multiple CPUs and IP blocks.
This development includes:

• RTL specification and design
• RTL and gate-level simulations
• Specification of test and validation suites
• Testbench development
• Development of hardware-software tests
• Coverage analysis of tests

Candidate Profile

• Engineer in electronics with 3/4 years of experience minimum

Skills and Competencies

• Digital design, VHDL RTL, Modelsim, full timing simulations, Specman e.
• Experience with SoC busses
• Low level software development: DSP and MCU (C & ASM).
• Low-level ARM and DSP programming a big plus
• Good team spirit
• Good communication skills
• Fluent english